Aaeon PFM-HDS Manuel d'utilisateur Page 53
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- Table des matières
- MARQUE LIVRES
- PFM-HDS 1
- Copyright Notice 2
- Acknowledgments 3
- Packing List 4
- Contents 5
- PC/104 Module PFM-HDS 10
- Chapter 13
- Component Side 15
- Solder Side 16
- 2.4 List of Jumpers 19
- 2.7 CRT Connector (CN1) 23
- 2.8 Audio Connector (CN2) 24
- 2.13 Clear CMOS (CN9) 27
- 2.17 USB2.0 Connector (CN13) 29
- 2.18 USB2.0 Connector (CN14) 29
- 2.23 SATA Connector (CN20) 31
- 2.24 AT/ATX Selection (CN21) 31
- 2.38 LAN Connector (LAN1) 41
- Chapter 43
- Setup Menu 46
- Setup submenu: Main 46
- Setup submenu: Advanced 47
- ACPI Settings 49
- RTC Wake Settings 50
- CPU Configuration 52
- IDE Configuration 53
- USB Configuration 54
- Serial Port 1 Configuration 56
- Serial Port 2 Configuration 57
- Serial Port 3 Configuration 58
- Serial Port 4 Configuration 59
- F81866 H/W Monitor 60
- Smart Fan Mode Configuration 61
- ISA Configuration 64
- IRQ Configuration 65
- Setup submenu: Chipset 66
- LVDS Panel Config 67
- South Bridge 69
- Setup submenu: Boot 70
- BBS Priorities 71
- Setup submenu: Security 72
- Setup submenu: Exit 73
- STEP4 - PCI to 78
- Appendix 82
- A.1 Watchdog Timer Registers 83
- AaeonWDTEnable (){ 85
- WDTClearTimeoutStatus(){ 86
- WDTReadByte(byte Register){ 86
- B.1 I/O Address Map 88
- B.3 IRQ Mapping Chart 91
- B.4 DMA Channel Assignments 91
- Appendix 92
- C - 3 94
- A ppendix 95
- PC/104 Module PFM-HDS 100
- E.3 Digital I/O Register 101
- Main(){ 102
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